outb               64 bootmain.c       outb(0x1F2, 1);   // count = 1
outb               65 bootmain.c       outb(0x1F3, offset);
outb               66 bootmain.c       outb(0x1F4, offset >> 8);
outb               67 bootmain.c       outb(0x1F5, offset >> 16);
outb               68 bootmain.c       outb(0x1F6, (offset >> 24) | 0xE0);
outb               69 bootmain.c       outb(0x1F7, 0x20);  // cmd 0x20 - read sectors
outb              135 console.c        outb(CRTPORT, 14);
outb              137 console.c        outb(CRTPORT, 15);
outb              153 console.c        outb(CRTPORT, 14);
outb              154 console.c        outb(CRTPORT+1, pos>>8);
outb              155 console.c        outb(CRTPORT, 15);
outb              156 console.c        outb(CRTPORT+1, pos);
outb               58 ide.c            outb(0x1f6, 0xe0 | (1<<4));
outb               67 ide.c            outb(0x1f6, 0xe0 | (0<<4));
outb               84 ide.c            outb(0x3f6, 0);  // generate interrupt
outb               85 ide.c            outb(0x1f2, sector_per_block);  // number of sectors
outb               86 ide.c            outb(0x1f3, sector & 0xff);
outb               87 ide.c            outb(0x1f4, (sector >> 8) & 0xff);
outb               88 ide.c            outb(0x1f5, (sector >> 16) & 0xff);
outb               89 ide.c            outb(0x1f6, 0xe0 | ((b->dev&1)<<4) | ((sector>>24)&0x0f));
outb               91 ide.c              outb(0x1f7, IDE_CMD_WRITE);
outb               94 ide.c              outb(0x1f7, IDE_CMD_READ);
outb              148 lapic.c          outb(CMOS_PORT, 0xF);  // offset 0xF is shutdown code
outb              149 lapic.c          outb(CMOS_PORT+1, 0x0A);
outb              187 lapic.c          outb(CMOS_PORT,  reg);
outb              153 mp.c               outb(0x22, 0x70);   // Select IMCR
outb              154 mp.c               outb(0x23, inb(0x23) | 1);  // Mask external interrupts.
outb               21 picirq.c         outb(IO_PIC1+1, mask);
outb               22 picirq.c         outb(IO_PIC2+1, mask >> 8);
outb               36 picirq.c         outb(IO_PIC1+1, 0xFF);
outb               37 picirq.c         outb(IO_PIC2+1, 0xFF);
outb               45 picirq.c         outb(IO_PIC1, 0x11);
outb               48 picirq.c         outb(IO_PIC1+1, T_IRQ0);
outb               52 picirq.c         outb(IO_PIC1+1, 1<<IRQ_SLAVE);
outb               62 picirq.c         outb(IO_PIC1+1, 0x3);
outb               65 picirq.c         outb(IO_PIC2, 0x11);                  // ICW1
outb               66 picirq.c         outb(IO_PIC2+1, T_IRQ0 + 8);      // ICW2
outb               67 picirq.c         outb(IO_PIC2+1, IRQ_SLAVE);           // ICW3
outb               70 picirq.c         outb(IO_PIC2+1, 0x3);                 // ICW4
outb               76 picirq.c         outb(IO_PIC1, 0x68);             // clear specific mask
outb               77 picirq.c         outb(IO_PIC1, 0x0a);             // read IRR by default
outb               79 picirq.c         outb(IO_PIC2, 0x68);             // OCW3
outb               80 picirq.c         outb(IO_PIC2, 0x0a);             // OCW3
outb               28 timer.c          outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
outb               29 timer.c          outb(IO_TIMER1, TIMER_DIV(100) % 256);
outb               30 timer.c          outb(IO_TIMER1, TIMER_DIV(100) / 256);
outb               24 uart.c           outb(COM1+2, 0);
outb               27 uart.c           outb(COM1+3, 0x80);    // Unlock divisor
outb               28 uart.c           outb(COM1+0, 115200/9600);
outb               29 uart.c           outb(COM1+1, 0);
outb               30 uart.c           outb(COM1+3, 0x03);    // Lock divisor, 8 data bits.
outb               31 uart.c           outb(COM1+4, 0);
outb               32 uart.c           outb(COM1+1, 0x01);    // Enable receive interrupts.
outb               60 uart.c           outb(COM1+0, c);